1. Field of the Invention
The present invention relates to an interrupt routing scheme, and more particularly to an interrupt controller, an apparatus including the interrupt controller and processor(s), and corresponding methods for processing interrupt request event(s) in a system.
2. Description of the Prior Art
For a system having multiple processors (also called microprocessors), issuing an interrupt request event to one of the processors is typically required in order to perform a service routine. When an interrupt request event is received by the processor whilst it is executing a main process, the processor will temporarily interrupt the main process under execution, and then execute the Interrupt Service Routine (ISR) specified by the interrupt request event corresponding to an interrupt input. In the system, interrupt inputs may be generated by multiple sources; since one processor cannot simultaneously execute multiple ISRs corresponding to the plurality of interrupt inputs, an interrupt controller is provided for receiving the various interrupt inputs, and routing the interrupt inputs to one or more of the processors. Currently developed routing schemes, however, cannot achieve a better and stable performance of the whole system under critical conditions when the processors become busy or unavailable during a specific time period.